Si5857DU
Vishay Siliconix
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
Maximum Junction-to-Ambient (MOSFET) b, f
t ≤ 5s
R thJA
43
55
Maximum Junction-to-Ambient (Schottky)
Maximum Junction-to-Case (Drain) (MOSFET)
b, g
Maximum Junction-to-Case (Drain) (Schottky)
t ≤ 5s
R thJC
R thJA
R thJC
9.5
49
13
12
61
16
°C/W
Notes:
a. Package limited.
b. Surface Mounted on FR4 board.
c. t ≤ 5 s.
d. See Solder Profile ( www.vishay.com/doc?73257 ). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection. Rework Conditions: manual soldering with a soldering iron is not
recommended for leadless components.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under Steady State conditions for MOSFETS is 105 °C/W.
g. Maximum under Steady State conditions for Schottky is 110 °C/W.
SPECIFICATIONS T J = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
V DS Temperature Coefficient
V GS(th) Temperature Coefficient
V DS
Δ V DS/TJ
Δ V GS(th)/TJ
V GS = 0 V, I D = - 250 μA
I D = - 250 μA
- 20
- 19
2.6
V
mV/°C
Gate-Source Threshold Voltage
V GS(th)
V DS = V GS , I D = - 250 μA
- 0.6
- 1.5
V
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current a
I GSS
I DSS
I D(on)
V DS = 0 V, V GS = ± 12 V
V DS = - 20 V, V GS = 0 V
V DS = - 20 V, V GS = 0 V, T J = 55 °C
V DS ≤ - 5 V, V GS = - 4.5 V
- 20
± 100
-1
- 10
ns
μA
A
Drain-Source On-State Resistance a
Forward Transconductance a
R DS(on)
g fs
V GS = - 4.5 V, I D = - 3.6 A
V GS = - 2.5 V, I D = - 1 A
V DS = - 10 V, I D = - 3.6 A
0.048
0.081
10
0.058
0.100
Ω
S
Dynamic b
Input Capacitance
C iss
480
Output Capacitance
Reverse Transfer Capacitance
C oss
C rss
V DS = - 10 V, V GS = 0 V, f = 1 MHz
125
90
pF
Total Gate Charge
Gate-Source Charge
Q g
Q gs
V DS = - 10 V, V GS = - 10 V, I D = - 5 A
V DS = - 10 V, V GS = - 4.5 V, I D = - 5 A
11
5.5
1.2
17
8.5
nC
Gate-Drain Charge
Q gd
1.8
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
R g
t d(on)
t r
t d(off)
f = 1 MHz
V DD = - 10 V, R L = 2.5 Ω
I D ? - 4 A, V GEN = - 4.5 V, R g = 1 Ω
9
11
42
33
20
65
50
Ω
Fall Time
Turn-On Delay Time
t f
t d(on)
50
5
75
10
ns
Rise Time
Turn-Off Delay Time
Fall Time
t r
t d(off)
t f
V DD = - 10 V, R L = 2.5 Ω
I D ? - 4 A, V GEN = - 10 V, R g = 1 Ω
15
25
10
25
40
20
www.vishay.com
2
Document Number: 73696
S09-2111-Rev. D, 12-Oct-09
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